1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a method for fabricating a capacitor.
2. Description of the Related Art
As the integration degree of semiconductor devices increases, the accompanying difficulty in manufacturing technology also increases. In the case of DRAMs, as the design rule parameters shrink, a process for manufacturing high aspect ratio storage nodes is useful.
In the process for forming a storage node, a mold layer is etched to form a hole forming an opening and a storage node is formed in the opening. At this time, in order to increase capacitance proportionally to an increase in height of the storage node, the height of the mold layer is to be increased. The mold layer is generally formed of oxide, and thus referred to as ‘mold oxide’. After the storage node is formed, the mold layer is removed by a wet dip-out process.
FIG. 1 is a diagram illustrating a conventional method for fabricating a capacitor.
Referring to FIG. 1, an interlayer dielectric layer 12 is formed over a semiconductor substrate 11, and a storage node contact plug 13 is formed. Subsequently, an etch stop layer 14 and a mold oxide layer 15 are formed over the interlayer dielectric layer 12. The mold oxide layer 15 and the etch stop layer 14 are sequentially etched to form an opening 16.
In order to secure sufficient capacitance, the aspect ratio of the storage node is set to 70 or more, which is considered to be a high aspect ratio.
In the conventional method of FIG. 1, as the height of the storage node is increased to secure capacitance, the depth of the opening 16 increases. Therefore, the etch profile of the opening 16 with a high aspect ratio may be sloped (as illustrated by an area denoted by reference numeral ‘17’) or the opening may not even be opened (as illustrated by an area denoted by reference numeral ‘18’). When the etch profile is sloped, the structural stability of the storage node decreases. In this case, the storage node may lean during a subsequent dip-out process.